Semiconductor integrated circuits are typically manufactured by forming an array of separate dies on a common semiconductor wafer. During processing, the semiconductor wafer is treated to form specified regions of insulating, conductive and semiconductor type materials. The ever increasing requirements for high density devices comprising conductive wiring patterns with increasingly smaller distances between conductive lines and small diameter vias in dielectric layers, particularly at high rates of production, pose a significant technological challenge. Conventionally, a conductive wiring pattern comprising a dense array of conductive lines is formed by depositing a metal layer, etching to form a conductive pattern and applying a dielectric material. Single and dual damascene techniques have also been employed to form openings in a dielectric layer which are subsequently filled with metal. The application of damascene techniques to the manufacture of semiconductor devices is disclosed in Joshi, "A New Damascene Structure for Submicrometer Interconnect Wiring," IEEE Electron Letters, Vol. 14, No. 3, Mar. 1993, pp. 129-132; Kaanta et al., "Dual Damascene: A ULSI Wiring Technology," Jun. 11-12, 1991, VMIC Conference, IEEE, pp. 144-152; Kenney et al., "A Buried-Plate Trench Cell for a 64-Mb DRAM," 1992 Symposium on VLSI Technology Digest of Technical Papers, IEEE, pp. 14-15; U.S. Pat. Nos. 5,262,354; and 5,093,279. After formation of the wiring pattern, planarization is effected as by chemical-mechanical polishing.
As shown in FIG. 1A, during an initial processing stage for forming an integrated circuit, a dielectric film 10 is deposited over a patterned conductive layer such as a metal 11. The object is to planarize steps 12 in dielectric layer 10 as shown in FIG. 1B. After deposition of layer 10, the portion thereof outside the trench must be removed. Such removal can be effected by plasma etching, or by a simplified faster and relatively inexpensive method known as chemical-mechanical planarization or polishing (CMP).
CMP is a conventional technique as disclosed in, for example, Salugsugan, U.S. Pat. No. 5,245,794; Beyer et al., U.S. Pat. No. 4,944,836; Youmans, U.S. Pat. No. 3,911,562. CMP is discussed in relation to earlier methods of fabricating metal interconnect structures by Kaufman et al., "Chemical-Mechanical Polishing for Fabricating Patterned W Metal Features as Chip Interconnects," J. Electrochem. Soc., Vol. 138, No. 11, Nov. 1991, pp. 3460-3464. U.S. Pat. Nos. 4,193,226 and 4,811,522 to Gill, Jr. and U.S. Pat. No. 3,841,031 to Walsh relate to CMP apparatus. Various problems associated with CMP are discussed by Ali et al., "Chemical-mechanical polishing of interlayer dielectric: A review," Solid State Technology, October 1994, pp. 63-68.
Basically, in employing a conventional CMP apparatus, semiconductor wafers having a dielectric layer applied thereon to be polished are mounted on a carrier assembly and placed on the CMP apparatus. A rotatable polishing pad is adapted to engage the semiconductor wafers carried by the carrier assembly. A chemical agent containing an abrasive, typically a slurry, is dripped onto the rotating polishing pad continuously during the CMP operation at a rate of about 50 to about 500 ml/min. while pressure is applied to the semiconductor wafers via the carrier assembly.
A typical CMP apparatus 100 is shown in FIG. 2 and comprises a rotatable polishing platen 102, polishing pad 104 mounted on platen 102, driven by microprocessor control motor (not shown) to spin at about 10 to about 100 RPM. Wafer 106 is mounted on the bottom of a rotatable carrier assembly 108 so that a major surface of wafer 106 to be polished is positionable to contact the underlying polishing pad 104. Wafer 106 and carrier assembly 108 are attached to a vertical spindle 110 which is rotatably mounted in a lateral robotic arm 112 which rotates the carrier assembly 108 at about 10 to about 75 RPM, preferably in excess of 20 RPM in the same direction as platen 102 and radially positions the carrier assembly on the platen. Robotic arm 112 also vertically positions carrier assembly 108 to bring wafer 106 into contact with polishing pad 104 and maintain an appropriate polishing contact pressure. Carrier assemblies are available which accommodate a plurality of wafers. A tube 114 opposite carrier assembly 108 above polishing pad 104 dispenses and evenly saturates the pad with an appropriate cleaning agent 116, typically a slurry.
As shown in FIG. 3, polishing pad 31 rotates in the direction of arrow 35, while carrier assembly 32 rotates in the direction of arrow 34, similar to the direction of arrow 35, but at a different speed than the polishing pad, while a downward force is applied to the carrier assembly 32 at 33 in a direction perpendicular to carrier assembly 32.
A polishing pad typically employed in a conventional CMP apparatus comprises a fibrous polymeric material, such as polyurethane and/or a polyester. One such type of fibrous polymeric polishing pad is IC 1000, commercially available in a pad set marketed as IC 1000/SUBA4 by Rodel of Newark, Del. It is difficult to uniformly planarize dielectric layers, doped and undoped, particularly dielectric layers having small diameter vias, e.g., less than about 0.5 microns, and dielectric layers comprising dense conductive patterns having interwiring spacings less than about 0.5 microns. It is also difficult to uniformly planarize a plurality of semiconductor wafers sequentially with a substantial degree of consistent uniformity. These problems stem from the difficulty in planarizing a dielectric layer on a semiconductor wafer to achieve a uniform removal rate across the dielectric surface, particularly at a high rate of removal.
The difficulty in achieving uniform planarization is a problem which is recognized in the semiconductor industry. Previous attempts to solve this problem focus upon improvements in consumable materials employed during CMP, such as the polishing pad and cleaning agent, or improvements in the hardware itself, such as the CMP apparatus. The difficulty in achieving a uniform removal rate across the surface of a semiconductor wafer, particularly at a high removal rate, is also recognized in the art. See, for example, Cote et al., U.S. Pat. No. 4,910,155, wherein a CMP technique is disclosed employing a pool of slurry at a temperature of 85.degree. F. to 95.degree. F. to economically improve uniformity by increasing polishing pad lifetime without introducing areas of locally incomplete polishing, e.g., bumps. The disclosed technique is said to require a break-in procedure which is less vigorous than conventional conditioning techniques and, thereby, extend the lifetime of the polishing pad. The slurry pool is obtained by providing a retaining wall or damn to increase the amount of slurry provided to the polishing pad. The amount of slurry sufficient to completely cover the polishing pad even when it is spinning during the CMP process, e.g., approximately 1/4" deep. In the method disclosed by Cote et al., when employing a pool of slurry, the polishing pad and wafer carrier or quill are reduced from 120 rpm to 15 to 30 rpm.
Notwithstanding the CMP technique disclosed by Cote et al., it is recognized in column 4, lines 44 et sec., that uniform removal rates were only achieved at about 500 .ANG. to 1,500 .ANG./min. Cote et al. report that uniform planarization of a dielectric layer on a semiconductor wafer, i.e., blanket planarization, could not be achieved at a removal rate above about 2,000 .ANG./min., with the adverse occurrence of nonuniformities, such as bumps. It was recognized that when planarizing an isolated portion of the surface of a semiconductor wafer, such as a passivation layer overlying a steep topographical feature, a localized removal rate of up to 6,000 .ANG./min. can be achieved without the formation of bumps. However, this is recognized as quite a different matter from planarizing the surface of a semiconductor wafer, i.e., blanket planarization vis-a-vis planarization of a localized topographical feature.
There exists in the semiconductor industry a need for a CMP technique for uniformly planarizing a dielectric layer on a semiconductor wafer at a high removal rate, e.g., in excess of about 2,500 .ANG./min., particularly for CMP a plurality of semiconductor devices sequentially with substantially consistent uniformity.